Electronic Design

Low-Density Parity Check Error Correction for Solid State Storage

Error Correcting Code (ECC) technology, such as Low-Density Parity Check codes, has been around longer than most of you reading this have been alive. The reason is ...
IEEE

Optimizing LDPC Decoding with ML-Assisted Signal Refinement for Next-Gen Communications

Abstract: Low-density parity-checks codes play a crucial role in ensuring reliable data transmission by correcting errors introduced by noisy communication channels. The study examines the performance ...
EDN

Low power LDPC decoder created using high level synthesis

HLS methodology allows the hardware design to be completed at a higher level of abstraction such as C/C++ algorithmic description. This provides significant time and cost savings, and paves the way ...
IEEE

A Local Re-Decoding Algorithm for LDPC-Coded Modulation With CCDMs

Abstract: This letter proposes to break trapping sets of the low-density parity-check (LDPC) codes used in an LDPC-coded modulation system that employs constant composition distribution matchers ...
Electronic Design

Interview: Kent Smith Addresses Error Correction And Flash Storage Technology

Figure 1. LDPC decoding latency can be minimized by using progressively stronger (and slower) forms of soft-decision (SLDPC) decoding only as needed when hard-decision (HDLPC) decoding fails. LSI ...
Design-Reuse

Flash Memory LDPC Decoder IP Core Available For Integration From Global IP Core

January 6, 2025 - Global IP Core Sales - In the Sum Product Algorithm (SPA) for LDPC decoding the messages are sent from the check nodes to bit nodes after the SPA steps which are (for one iteration): ...
Design-Reuse

Creonic to Supply New LDPC Decoder and Encoder IP Cores for CCSDS Standard

Kaiserslautern, Germany, Apr. 30 2015 – Creonic GmbH, a leading IP core provider for communications, announced today the release of their new CCSDS LDPC encoder and decoder IP cores for the satellite ...