I'm using the LZ4 compression core for my custom logic. However, after running the bitstream generation with tcl, it is hard to reconfigure the ports due to the unclear Verilog code generated from the ...
Could not load file or assembly 'lz4.x64' or one of its dependencies. An attempt was made to load a program with an incorrect format. === Pre-bind state information === LOG: DisplayName = lz4.x64 ...
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