Design-Reuse

Guidelines for Verilog-A Compact Model Coding

The Verilog-AMS hardware description language [1] includes extensions dedicated to compact modeling, but does not define a reserved subset for compact modeling. This lack of specification combined ...
GitHub

Golay Code Verilog Implementation

An implementation of an extended binary Golay encoder and sophisticated low-resource decoder in Verilog. Code in question: [24,12,8]. Corresponding group: G12. This code maps 12 input bits to 24 ...
EDN

Assertion Methodologies for Verilog Design

Sometimes good ideas take a while to catch on in engineering practice. The use of in-line assertions to document assumptions and check for problems in RTL code is one such idea. Long ago proposed for ...
Design-Reuse

AMIQ EDA Releases the DVT Debugger Add-On Module for the e language, SystemVerilog, Verilog ...

AMIQ EDA, a pioneer in integrated development environments (IDEs) for hardware design and verification and a provider of platform-independent software tools for efficient code development, today ...
EDN

Putting the R in RTL : Coding Registers in Verilog and VHDL

Many years ago, when I was a young man and the Boston Red Sox had just lost the 1986 world series, controversy stalked the land of hardward development. A new technology called Register Transfer ...
GitHub

"Dotting" into a Module to read out public fields generates broken Verilog code

So this may be a mortal sin, but I'm trying to "dot" into a Module to read some of its public fields (instead of using it's I/O bundle). The issue is, for debug/printf purposes, I need to read the ...
Hackaday

FPGA Testbenches Made Easier

You finally finish writing the Verilog for that amazing new DSP function that will revolutionize human society and make you rich. Does it work? Your first instinct, of course, is to blow it into your ...