GitHub

Golay Code Verilog Implementation

An implementation of an extended binary Golay encoder and sophisticated low-resource decoder in Verilog. Code in question: [24,12,8]. Corresponding group: G12. This code maps 12 input bits to 24 ...
EDN

Assertion Methodologies for Verilog Design

Sometimes good ideas take a while to catch on in engineering practice. The use of in-line assertions to document assumptions and check for problems in RTL code is one such idea. Long ago proposed for ...
Design-Reuse

AMIQ EDA Releases the DVT Debugger Add-On Module for the e language, SystemVerilog, Verilog, and VHDL

AMIQ EDA, a pioneer in integrated development environments (IDEs) for hardware design and verification and a provider of platform-independent software tools for efficient code development, today ...
Hackaday

FPGA Testbenches Made Easier

You finally finish writing the Verilog for that amazing new DSP function that will revolutionize human society and make you rich. Does it work? Your first instinct, of course, is to blow it into your ...
GitHub

advent-of-code-2025-fpga

This design solves Part 2 of Day 10 in Advent of Code 2025. In summary, there are buttons that increase the "joltage" levels of the designated machines by 1. The goal is to find the minimum number of ...
Design-Reuse

Reusing Verilog IP Cores in SystemC Environment by V2SC

SystemC 2.1 supports all hardware concepts introduced by HDLs such as Verilog and VHDL. V2SC proposes a methodology for automatic conversion of Verilog 2001 constructs into SystemC 2.1 language. This ...